The integration of the semiconductor device has hitherto been achieved mainly by miniaturizing transistors. However, miniaturization of transistors has come to the limit, and when the transistors are attempted to be more miniaturized, there is a risk that the semiconductor device does not operate correctly due to the short-channel effect and the like.
As a method of basically solving this problem, there has been proposed a method of three-dimensionally processing a semiconductor substrate, thereby three-dimensionally forming a transistor. A three-dimensional transistor using a silicon pillar extending perpendicularly to the main surface of the semiconductor substrate as a channel has an advantage in that an occupied area is small and that a large drain current is obtained by a complete depletion. This three-dimensional transistor can be also used for a closest layout of 4F2 (see Japanese Patent Application Laid-open Nos. 2003-303901, H5-136374, H6-209089, H9-8295, and 2002-83945).
In case of using a vertical transistor having a silicon pillar as a cell transistor of a semiconductor memory device, it is general that one of diffusion layers works as a source or drain is connected to a bit line and the other diffusion layer is connected to a memory element (a cell capacitor in a DRAM). Usually, a memory element like a cell capacitor is laid out above the cell transistor. Therefore, the memory element is connected to an upper part of the silicon pillar, and a bit line is connected to a lower part of the silicon pillar.
However, because a semiconductor substrate is positioned at the lower part of the silicon pillar, it is not easy to form a bit line on the lower part of the silicon pillar, and the process becomes complex in many cases.